//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
//Date        : Sat Nov  5 10:16:18 2022
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module zoom
(
   inout       [14:0]            DDR_addr,
   inout       [2:0]             DDR_ba,
   inout                         DDR_cas_n,
   inout                         DDR_ck_n,
   inout                         DDR_ck_p,
   inout                         DDR_cke,
   inout                         DDR_cs_n,
   inout       [3:0]             DDR_dm,
   inout       [31:0]            DDR_dq,
   inout       [3:0]             DDR_dqs_n,
   inout       [3:0]             DDR_dqs_p,
   inout                         DDR_odt,
   inout                         DDR_ras_n,
   inout                         DDR_reset_n,
   inout                         DDR_we_n,
   inout                         FIXED_IO_ddr_vrn,
   inout                         FIXED_IO_ddr_vrp,
   inout       [53:0]            FIXED_IO_mio,
   inout                         FIXED_IO_ps_clk,
   inout                         FIXED_IO_ps_porb,
   inout                         FIXED_IO_ps_srstb,
   input                         hdmi_clk_p,
   input                         hdmi_clk_n,
   input       [2:0]             hdmi_dat_p,
   input       [2:0]             hdmi_dat_n,
   inout                         hdmi_scl,
   inout                         hdmi_sda,
   output                        hdmi_cec,
   input                         hdmi_hpd,
   output                        hdmi_out_en
);

wire                             clk_100m;
wire                             hdmi_sda_i;
wire                             hdmi_sda_o;
wire                             hdmi_sda_t;
wire                             hdmi_scl_i;
wire                             hdmi_scl_o;
wire                             hdmi_scl_t;
wire                             clk_200m_rstn;
wire                             clk_200m;
wire  [23:0]                     vid_data;
wire                             vid_vde;
wire                             vid_hsync;
wire                             vid_vsync;
wire                             vid_clk;

assign hdmi_out_en = 1'b0;

clk_wiz_0 u_clk_wiz_0
(
   .clk_out1                     ( clk_200m ),
   .reset                        ( 1'b0 ),
   .locked                       ( clk_200m_rstn ),
   .clk_in1                      ( clk_100m )
);

dvi2rgb
#(
   .kClkRange                    ( 1 ),
   .kIDLY_TapValuePs             ( 78 ),
   .kIDLY_TapWidth               ( 5 )
)
u_dvi2rgb
(
   .TMDS_Clk_p                   ( hdmi_clk_p ),
   .TMDS_Clk_n                   ( hdmi_clk_n ),
   .TMDS_Data_p                  ( hdmi_dat_p ),
   .TMDS_Data_n                  ( hdmi_dat_n ),

   .RefClk                       ( clk_200m ),
   .aRst                         ( ~clk_200m_rstn ),
   .aRst_n                       ( clk_200m_rstn ),

   .vid_pData                    ( vid_data ),
   .vid_pVDE                     ( vid_vde ),
   .vid_pHSync                   ( vid_hsync ),
   .vid_pVSync                   ( vid_vsync ),
   .PixelClk                     ( vid_clk ),

   .SerialClk                    ( ),
   .aPixelClkLckd                ( ),
   .pLocked                      ( ),

   .SDA_I                        ( hdmi_sda_i ),
   .SDA_O                        ( hdmi_sda_o ),
   .SDA_T                        ( hdmi_sda_t ),
   .SCL_I                        ( hdmi_scl_i ),
   .SCL_O                        ( hdmi_scl_o ),
   .SCL_T                        ( hdmi_scl_t ),

   .pRst                         ( ~clk_200m_rstn ),
   .pRst_n                       ( clk_200m_rstn )
);

system u_system
(
   .CLK_100M(clk_100m),
   .DDR_addr(DDR_addr),
   .DDR_ba(DDR_ba),
   .DDR_cas_n(DDR_cas_n),
   .DDR_ck_n(DDR_ck_n),
   .DDR_ck_p(DDR_ck_p),
   .DDR_cke(DDR_cke),
   .DDR_cs_n(DDR_cs_n),
   .DDR_dm(DDR_dm),
   .DDR_dq(DDR_dq),
   .DDR_dqs_n(DDR_dqs_n),
   .DDR_dqs_p(DDR_dqs_p),
   .DDR_odt(DDR_odt),
   .DDR_ras_n(DDR_ras_n),
   .DDR_reset_n(DDR_reset_n),
   .DDR_we_n(DDR_we_n),
   .FIXED_IO_ddr_vrn(FIXED_IO_ddr_vrn),
   .FIXED_IO_ddr_vrp(FIXED_IO_ddr_vrp),
   .FIXED_IO_mio(FIXED_IO_mio),
   .FIXED_IO_ps_clk(FIXED_IO_ps_clk),
   .FIXED_IO_ps_porb(FIXED_IO_ps_porb),
   .FIXED_IO_ps_srstb(FIXED_IO_ps_srstb)
);

endmodule
